Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes

Optical interconnects for system-in-package applications can be designed for various bit rates. In this paper, an optimization study is conducted to find the optimal parameters for electrooptical links, based on a silicon photonic technology. We focus on the bit rate to achieve highest possible power efficiencies. This paper takes all the elements of an electrooptical link into account: serialization stage, ring-resonator-based modulator, thermal stabilization, modulator driver, laser, receiver, deserialization stage, and clock-phase generation. The optimization is based on a simulation-supported database for single-ended transimpedance amplifiers (TIAs). For all the other, elements of the link simulation-based power consumption models are presented. Furthermore, an analytical solution for the TIA bandwidth and bit rate relationship is derived based on the system jitter, the TIA noise, transimpedance, bandwidth and minimal output swing, and the available input signal. Optimal bit rates are derived and discussed for a 65-nm CMOS and a 28-nm fully depleted silicon-on-insulator technology. We found that the optimal bit rates increase with more aggressive technology scaling and smaller photodiode capacitances, but decrease if lower static power consumptions can be achieved (e.g., by efficient thermal tuning of ring-resonator modulators). We conclude that further research should aim for lower tuning powers instead of higher speed.