Improving SRAM test quality by leveraging self-timed circuits

As process technology continues to scale, SRAM test quality has become a growing concern in modern System-on-Chips. Ensuring high test quality while keeping costs low requires increasingly effective memory test solutions. This paper proposes the reuse of self-timing mechanisms that are integrated in many state-of-the-art SRAMs as a programmable DFT solution to improve the defect coverage of memory test algorithms. Its effectiveness is analyzed based on the injection of resistive-open defects inside SRAM core-cells. Simulation results of an industrial 28nm memory design show that the proposed test solution increases the coverage of studied defects by up to 30% dependent on their location, while not requiring extra circuitry inside the SRAM.