Exploiting more parallelism from write operations on PCM

The size of write unit in PCM, namely the number of bits allowed to be written concurrently at one time, is restricted due to high write energy consumption. It typically needs several serially executed write units to finish a cache line service when using PCM as the main memory, which results in long write latency and high energy consumption. To address the poor write performance problem, we propose a novel PCM write scheme called Min-WU (Minimize the number of Write Units). The key idea behind Min-WU is to minimize the number of serially executed write units in a cache line service through sFPC (simplified Frequent Pattern Compression), eRW ( efficient Reordering Write operations method) and fWP (fine-tuned Write Parallelism circuits). Using Min-WU, the zero parts of write units can be indicated with predefined prefixes and the residues can be reordered and written simultaneously under power constraints. Experimental results under PARSEC 2.0 workloads show that Min-WU reduces 32.5% running time and 48% energy as well as 44% latency compared with the conventional write scheme. When combined with partly data flip, the variation of Min-WU (Min-WU-PF) yields 12% running time reduction, 23% energy saving and 22% latency reduction compared with state-of-the-art Flip-N-Write.