Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache

Write reliability is one of the major challenges in design of spin-transfer torque random access memory (STT-RAM) caches. To ensure design quality, error correction code (ECC) scheme is usually adopted in STT-RAM caches. However, it incurs significant hardware overhead. In observance of the dynamic error correcting requirements, in this work, we propose Sliding Basket - an adaptive ECC scheme to suppress the runtime write failures of STT-RAM cache with minimized hardware cost. Our simulation results show that compared to the STT-RAM caches with conventional ECC scheme, applying Sliding Basket can achieve up to 80.2% saving in ECC bit overhead, comparable write reliability and even better system performance.