Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs

This paper presents an analytic and experimental study on a simultaneously bi-directional (SBD) TSV interconnect capable of energy and area efficient 3D-IC vertical signaling. We first explore TSV channel characteristics that differ from well-known off-chip channel properties, then analyze circuit design tradeoffs for SBD TSV signaling in terms of energy, bandwidth and noise margin. Based on this analysis, we propose a novel SBD TSV signaling circuit optimized for our system-level design goals and given TSV technology. Measurement results on a 28nm CMOS test chip show that the proposed SBD TSV interconnect enables 10.3-31.1% lower energy at 34.4% less area than two equivalent uni-directional TSVs. Although our single SBD TSV has 12.5% lower bandwidth than two uni-directional TSVs, the SBD TSV can support up to 9.1Gb/s/TSV bi-directional signaling (i.e. 4.55GHz maximum clock speed) at 1.05V.