Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects

Silicon photonic interconnect (SPI) is a promising candidate for the communication infrastructure in multiprocessor systems-on-chip (MPSoCs). When employing SPIs with wavelength-division multiplexing (WDM), it is required to precisely match different devices, such as photonic switches, filters, etc, in terms of their central wavelengths. Nevertheless, SPIs are vulnerable to fabrication non-uniformity (a.k.a. process variations), which influences the reliability and performance of such systems. Understanding process variations helps develop system design strategies to compensate for the variations, as well as estimate the implementation cost for such compensations. For the first time, this paper presents a computationally efficient and accurate bottom-up method to systematically study different process variations in passive SPIs. Analytical models to study the impact of silicon thickness and waveguide width variations on strip waveguides and microresonator (MR)-based add-drop filters are developed. Numerical simulations are used to evaluate our proposed method. Furthermore, we designed, fabricated, and tested several identical MRs to demonstrate process variations. The proposed method is applied to a case study of a passive WDM-based photonic switch, which is the building block in passive SPIs, to evaluate its optical signal-to-noise ratio (OSNR) under different variations. The efficiency of our proposed method enables its application to large-scale SPIs in MPSoCs, where employing numerical simulations is not feasible.