Memory Bandwidth Extension through Tri-Level Signaling

A DDR-compatible signaling scheme is presented to increase memory bandwidth while accommodating the limitations of the DRAM transistor. Key features of the proposal include the addition of a third signal level between VOH and VOL, and an encoding scheme which maps three binary inputs into a pair of tri-level signals for transmission. The mapping of three bits to two pins increases per-pin bandwidth by 50% without increasing the clock frequency, which relaxes the demand on the DRAM transistor and data capture timing while reducing AC power.