Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM

Design techniques for 3-D SoC stacked with a Wide I/O DRAM with through silicon via (TSV) technology were developed. Some of the developed techniques were applied to design a Wide I/O DRAM controller chip. Micro-I/O cells and area efficient decoupling capacitor cells are implemented in between the fine pitch TSV array. Test circuitry for pre-bonding TSV tests are embedded in the micro-I/O cells with small area overhead. In order to reduce
${\rm V}_{\rm min}$
degradation induced by 512 DQs simultaneous switching noise, we introduce a package-board impedance optimization scheme utilizing a full digital noise monitor. We also developed a thermal aware memory control technique to adaptively change the refresh rates per channel, which are hot due to SoC hotspots. We achieved 12.8 GB/s operation, while I/O power was reduced by 89% compared to LPDDR3.