Forced Current Balancing of Parallel-Connected SiC JFETs During Forward and Reverse Conduction Mode

In this paper, a thorough investigation on the parallel connection of the latest generation vertical trench silicon carbide (SiC) junction field-effect transistors (JFETs) during forward and reverse conduction is performed. Both enhancement and depletion mode SiC JFETs are examined, regarding their static and dynamic characteristics. A parametric analysis on the current sharing, reliability, and effectiveness of the parallel connection is carried out. Current asymmetry over the different JFETs is monitored via series-connected current transformers. A forced current balancing technique during forward conduction mode is achieved by controlling the time delay of the gate signal through a low-cost digital signal controller. The drain current mismatch during reverse conduction is also studied and addressed by applying similar techniques as in the forward conduction, or by adding an antiparallel power diode. The performance of paralleled JFETs is validated through simulation and experimental results at room temperature and 150 °C.