Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays

Large-scale 3D crossbar arrays can enable both high-density Storage Class Memory (SCM) and novel non-Von Neumann computation. Such arrays require each nonvolatile memory (NVM) element to have its own non-linear Access Device (AD), to pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Typically, power consumption during write, not read margin, is the most stringent constraint for large 1AD+1R crossbar arrays. We extend our circuit-level SPICE simulations-previously performed just for large arrays of an AD based on Cu-containing Mixed-Ionic-Electronic-Conduction (MIEC)-materials together with a generic NVM element (+1R)-to three additional diode-like ADs as well as three threshold-switching ADs. We show that the suitability of an AD for 1AD1R memories is strongly dependent upon both nonvolatile memory (NVM) and circuit parameters, as well as the AD's own intrinsic properties. We find that building large arrays ( ≥ 1 Mb) with ≥ 10 μA NVM current is only possible for MIEC ADs and moderate NVM switching voltage ( ≤ 1.2 V). None of the ADs studied here support larger NVM switching voltage ( ≥ 1.2 V) unless switching current is ≤ 10 μA. The effects of line resistance, low-current (10-100 pA) bias condition, stacking two ADs vertically, and reductions in TVS threshold current are all studied. The particular AD parameters that would need to be improved to affect each AD's prospects are discussed.