A 16-bit 4 MSPS DAC for lock-in amplifier in 65nm CMOS

A 16-bit (5+11) segmented digital-to-analog converter (DAC), based on a voltage mode R-2R topology that is able to derive high resolution and high performance, in terms of INL and DNL, and less area and power consumption comparing with conventional DACs. It is designed and simulated in 65nm CMOS process. A current compensating technique is used to achieve good dynamic performance. The 16 bit R-2R DAC operates up to 4 MHz. The simulated differential and integral non-linearity (DNL and INL) are within +0.007, -0.043 LSB and +0.07/-0.267 LSB, respectively. The DAC is designed for a single-chip lock-in amplifier circuit.