High-Resolution On-Chip $S$ -Band Radar System Using Stretch Processing

In this paper, an S-band radar system that uses stretch processing is developed at the chip level. The novelty in this paper lies in providing an integrated, compact and miniaturized high-performance S-band radar system chipset. The radar has many characteristics that ensure high performance: 1) a wide bandwidth signal (600 MHz) that provides high resolution to distinguish between close objects; 2) an usage of stretch processing, which dramatically reduces the required sampling rates and relaxes the specifications of analog-to-digital converters; 3) high dynamic range (58 dB) that allows weak signals to be detected from targets masked by the high levels of clutter (such as snow and rain); 4) multiple receiver channels that enable digital antenna beamforming at the receiver to mitigate any strong interferer; and 5) operation in the S-band (2-4 GHz) that provides high immunity against clutter in long range surveillance applications. The architecture study revealed a super-hetrodyne modulator and receiver architecture offered the best solution. The high-order filters were pushed off-chip to reduce silicon area, reduce power consumption, and improve filtering results. The circuit-level design focused on designing the receiver blocks. The design included a high linearity quad passive mixer, IF cascode and common source amplifiers, and a negative-gm voltage controlled oscillator. The total receiver system of the radar chipset was designed and simulated at the circuit level on IBM 180-nm CMOS technology. To the best knowledge of the authors, this is the first integrated and smallest high-performance S-band radar to be designed.