CMOS current starved voltage controlled oscillator circuit for a fast locking PLL

Two novel voltage controlled oscillators (CSN-VCO and CSD-VCO) have been proposed in this paper. CSN-VCO has been designed with 20 transistors while CSD VCO with 24 transistors. It has been observed that CSN-VCO could operate in the frequency range from 0.066 to 2.2 GHz, and CSD VCO could operate from 0.047 to 2.5 GHz. Tuning range for these VCOs are determined to be 97 %, and 98.2 % while the values of gain obtained are 8.94 and 10.2 GradV−1 respectively. Phase noise analysis has been performed and the phase noise contribution by CSN-VCO and CSD VCO are found to be −126 and −129 dBc/Hz @ 1 MHz respectively. Prototype has been designed in Cadence virtuoso environment and implemented using GPDK090 library of 180 nm technology with a supply voltage of 1.8 V. Simulation of transfer function of PLL built with the VCOs has been done in MATLAB and the step response has been compared with the circuit simulation results from Cadence. Lock time as low as 355 ns and 313 ns have been achieved for the CSN-VCO and CSD-VCO respectively.