Generic system for characterization of BER and JTOL of high speed serial links

A generic system for Bit Error Rate (BER) and Jitter tolerance (JTOL) characterization of Physical Layers (PHY) for high speed serial links is developed and demonstrated. Proposed system architecture is configurable to suit the needs of various physical layers supporting different data rates and targeting various end applications. This system consists of jitter generation methodology using off-the-shelf equipments and BER analyzer implemented in FPGA kit and software for overall control of instrumentation and FPGA. Unlike loopback based industry solutions (e.g. BER Testers) where received data is transmitted back to the tester for BER analysis, this solution uses only the receiver block and thus it is suitable for high speed links which use same channel for both transmit and receive, wherein loop back possibility does not exist. It offers an added advantage of “true receiver only” characterization, since transmitter is eliminated from the path used in testing. It is capable of generating customized data patterns with random and deterministic components of timing jitter in a calibrated manner to measure JTOL. The results of JTOL tests performed using this system on different USB2.0 and MIPI MPHY Gear3B physical layers are presented in later part of the paper.