An emulation of transparent interface design based on TCP/IP implemented onto FPGA of an Altera Nios® Board

A TCP/IP-based interface design has been designed, and the interface can process data based on the Ethernet IEEE 802.3 Standard. This interface is able to identify Ethernet Frame IEEE 802.3, Header of LLC 802.2, Header and the Packet Data of IP Datagram. In addition, the interface can perform simple encryption process, and renew FCS (Frame Check Sequence) data of an ethernet frame. After the interface design had been simulated, it was implemented onto Altera Stratix EP1S10F780C6ES FPGA of an Altera Nios® Board. The interface's synthesis result shows that the interface's internal frequency is up to 78.01 MHz. Moreover, the implementation result was verified using SignalTap II Logic Analyzer. The interface functions as an emulator properly which can operate in half duplex mode.