Analog performance of n- and p-FET SOI nanowires including channel length and temperature influence

This work aims to present the analog performance of silicon n-type and p-MOSFET SOI nanowires. Analog parameters are shown at room temperature for both n- and p-type, long and short channel devices with different channel width. Results for long channel n-MOS nanowires are investigated for the first time for low temperatures down to 100K. Moreover, an analysis is shown comparing the intrinsic voltage gain in nanowires and quasi-planar transistors. The mobility dependence on the temperature is found to be the key parameter to describe the behavior of both transconductance and output conductance when decreasing temperature.