Design and analysis of a 16-bit 10MHz pipeline ADC in 0.25μ CMOS

This paper discusses the design and analysis of a 16-bit 10MHz pipeline Analog to Digital Converter (ADC). A system and circuit level design of each component of the ADC was created in Cadence. Features of ADC were simulated in Matlab to test and examine its basic functionality. Transient analysis of the design was conducted to verify the performance of the ADC. Methods to correct non-linarites were identified and investigated. The goal of this Major Qualifying Project is to design and fabricate a 16-bit 10MHz Pipeline Analog to Digital Converter (ADC) using 0.25μm CMOS. The motivation for designing a Pipeline ADC comes from the desire to characterize and test the functionality of the novel "Split ADC" Architecture concept [3] using a non-algorithmic ADC. We successfully characterized the System-level functionality of a Pipeline ADC by simulating its features through Matlab. A major part of the analog subsystem of the ADC was designed in Cadence. The simulation work corroborates with our theory and helped us to analyze the design block. It has provided us an opportunity to compare and contrast the ideal and non-ideal behavior of an ADC. Once the layout of the IC has been designed and fabricated, we shall move on to further work needed for data acquisition using a software package similar to LabView or Python.