Implementation of Viterbi coder for text to speech synthesis

This paper talks about designing an efficient Viterbi coder which can be used for Text to Speech synthesis (TTS). Today numerous applications uses Text to Speech synthesis (TTS) and Viterbi coder plays a key role in producing the synthesized output. Viterbi algorithm includes numerous iterations to produce the output and hence power utilization is more. We propose a technique which uses a memory access technique along with pipelined precomputation to reduce the power utilization and makes a trade off with speed. Here the overall power consumed by memory is 17 mw less than that of the power consumed by circuit used in the system.