FPGA-based Design of a Hearing Aid with Frequency Response Selection through Audio Input

Hearing aids provide frequency-selective amplification to compensate for the elevated hearing thresholds and automatic volume control to partly compensate for the significantly reduced dynamic range of hearing. The response selection controls of these devices are not easy to access during their normal use. To address this problem, an FPGA-based design of a hearing aid is presented, with frequency response selection by DTMF coded sound from a hand-held device without using switches, ports, or additional hardware. The audio input is given to two parallel processing blocks. The first block is a DTMF detector employing Goertzel algorithm and outputs control bits for selecting one of the pre-stored responses. The second block processes the signal for frequency-selective amplification and produces the audio output. The filter is designed as an FIR filter with its magnitude response approximating the product of the responses required for hearing-loss compensation and noise attenuation. It is efficiently realized using a processing architecture employing sequential multiply-accumulate operations. The design is implemented using FPGA "Altera Cyclone IV EP4CE115F29C7" and an audio codec and verified for satisfactory operation.