A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA

Soft output Viterbi detectors (SOVA) are universally used in all communication receivers within the digital back-end circuitry for mitigating intersymbol interference. Current implementations of the SOVA detector are based on uniform quantization using register exchange logic or with a trace back approach. In this paper, we investigate the design architecture and performance analysis of a SOVA detector based on non-uniform quantization. The proposed detector was synthesized and place and routed using Xilinx tool chain and implemented on Kintex-7 XC7K325T field programmable gate array (FPGA) kit. Implementation results in FPGA shows that our proposed architecture results in a 10.25% reduction in the total number of slice registers, 8.35% reduction in the number of slice look-up table (LUT) and reduction in the critical path delay leading to an estimated throughput of 2.15 Gbps with no performance loss compared to the uniform quantization scheme.