Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing

Tunnel FETs (TFETs) as steep slope devices have attracted much attention for designing energy efficient digital systems at scaled supply voltages. In this paper, we propose a circuit/architectural co-design approach for designing reliable and energy efficient adder cells for new computing platforms at supply voltages as low as 0.1V. At circuit level, widely used XOR gates such as 6T and 8T designs are explored and at the architectural level, adder cells with static CMOS like design (28T), tarnsmission gate design (24T), XOR based design (22T and 18T), and MUX based design (MBFA-22T) have been considered. The performance of all TFET designs have been benchmarked with 20nm double gate Si Fin FET technology. TFET designs have lower energy and energy delay product (EDP) due to TFET's steep sub threshold slope characteristics at 0.1V. 18T design is more energy efficient with slight trade-off in logic swing (i.e., robustness) and 22T and 28T designs are more robust and optimal energy efficient options.