Accurate and Efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits

Virtual ground voltage (Vgnd) has been used for fine grained optimization of power gated digital circuits. In this paper, we analyze the potential sources of error in dynamic characteristics of Vgnd due to inaccurate models as well as under-estimation of input voltages of CMOS gates in logic circuits. We propose a piecewise simulation based model for dynamic Vgnd estimation, which further needs capacitance models to be characterized at V gnd node. These capacitance models are used in conjunction with leakage current models to develop dynamic Vgnd model. Average error of less than 0.5% compared to 4.2% of previously reported models is achieved when compared to HSPICE results on ISCAS'85 benchmark circuits. On an average, our proposed model is 30 × efficient than HSPICE for dynamic V gnd estimation during mode transition.