A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss

A low Vmin, 6T-SRAM is realized in 28nm UTBB (Ultra-Thin Body and BOX) FDSOI technology using read and write assist methods. We could reduce the Vmin of SRAM cell to 0.5V for the 0.120um2 high density 6T-SRAM. Read margin of the SRAM cell is recovered using a compensated under driven word line scheme. Write assist is realized using negative bit-line approach. Bit-line is pulled to a required negative value in order to provide sufficient assistance for the write operation. Required word line under drive is 90mV to ensure correct read operation. For write assist, the undershoot requirement is 114mV. We could achieve a performance of 1.2MHz at 0.5V and 40MHz at 0.6V for a 288Kb capacity SRAM with 2K words of 144bits width. The area overhead of the read and write assist scheme is 1.0 percent and 2.5 percent respectively.