Logic Synthesis in Reversible PLA

Reversible logic have been motivated by consideration of zero-energy computation. Re-configurability and structural regularity of Programmable Logic Devices caused wide use of it by the logic designers. In this paper, we propose a design algorithm for a PLA (Programmable Logic Array) with a newly designed low cost 3 × 3 reversible NMG (New Mux Gate) circuit for implementing multi-output ESOP (Exclusive-OR Sum of Product) functions. In addition, we propose a heuristic to sort and to realize the product terms of ESOP functions in order to share the internal sub-products to reduce the number of gates in the proposed circuit. The proposed algorithms make the design efficient with improvement 9.05% in number of gates, 25.5% in garbage count and 14.5% quantum cost metric than existing techniques averagely. Performance is also analyzed by using MCNC benchmark circuits.