Energy Efficient and Congestion-Aware Router Design for Future NoCs

Network-on-Chip (NoC) has been well accepted for energy efficient on-chip communications for many-core systems. But, a NoC router consumes significantly high power and the number of routers increases linearly with number of cores. For large scale applications, the cumulative power dissipation in routers is comparatively high. Of all router components, input buffers consume significant amount of power. Additionally, removing buffers from NoC router leads to performance degradation and network congestion overhead. To make NoC energy efficient without increasing network congestion, in this paper we approach the router architecture by utilizing the Marching Memory buffers instead of traditional register based buffers for better energy efficiency and performance. Energy analysis on a 16-core mesh based NoC topology running PARSEC and SPLASH-2 benchmark application traffic shows that in the presence of Marching Memory buffer, our proposed router reduces the total energy by 18% and 25% respectively with negligible performance overhead.