Emulation - Smart Way of Power Estimation and Power Aware Verfication

Summary form only. Shrinking geometries, increasing complexities of SoCs, and ever increasing battery operated devices have necessitated extremely complex methods to minimize Static and Dynamic Power to avoid heating issues, high activity hot spots - which translate to functional issues or burnout. Therefore, there is a need for Power Aware based Functional Verification right from the RTL stage to detect and avoid potential post spin issues. Power Management Specification to reduce Static and Dynamic power, involves power gating, voltage scaling, multi-voltage domain interactions - which require cells such as isolation, level-shifter, state-retention, and switches. UPF (IEEE1801) provides a way for power management block to be specified right from the RTL level. Pre-estimation of power dissipation is typically based on waveforms, generated over complete tests, fed as input to power analysis tools for power computation. Such data would be huge and requires very long time to generate which prompts the designers to run smaller tests and extrapolate the results. This leads to inaccuracy and post spin issues. This tutorial presents the smart way of leveraging the strength of emulator to test a power aware model for the right power sequence as well as quick and accurate power estimation without incurring any capacity overhead.