Low Power Magnetic Flip-Flop Optimization With FDSOI Technology Boost

The planar ultrathin body and buried oxide fully depleted silicon-on-insulator (FDSOI) technology is one of the proper candidates to replace bulk CMOS due to its high volume, low cost, and lower power. In this paper, we investigate the performance of hybrid magnetic-MOS non-volatile (NV) magnetic flip-flops (MFFs) in the FDSOI technology. The NV-MFF performance parameters, e.g., active power, leakage power, and sensing delay, are optimized with selected design vectors: supply voltage (V
_dd
), forward body bias (FBB), and poly bias (PB). NVFF reliability can be improved by FBB performance compensation. The perpendicular magnetic anisotropy spin-torque transfer magnetic tunnel junction (MTJ) is used to design the MTJ/MOS hybrid MFFs. Two typical MFF circuits: master-slave MFF and multiplexing sense amplifier-based MFF are implemented and analyzed with the 28 nm FDSOI technology. The simulation results show that the MFFs in the FDSOI technology feature high energy efficiency and enhanced reliability. The energy efficiency of MFF is guaranteed by the proper selection of V
_dd
and FBB voltage. PB is useful for low leakage power design, with the tradeoff of additional sensing delay. The highest PB and the lowest BB transistor configuration lead to large improvements in leakage power consumption.