An efficient FPGA based de-noising architecture for removal of high density impulse noise in images

Impulse noise is introduced into images in the process of image acquisition and transmission. High density impulse noise suppression using median type filters result worst where as these execute better to suppress the low density impulse noise from corrupted images. Some state of art methods are able to remove high density impulse noise from corrupted images but sometimes the detail of images are changed a bit and make execution time higher. In this paper, we propose an efficient approach to suppression algorithm and its VLSI design for suppression of impulse noise with higher density (up to 99%). To reach the aim of making cost effective efficiently executable design, an FPGA based reconfigurable architecture is proposed. The proposed architecture is working with two different stages — normal and conditional sorting followed by decision based output selection unit. In decision based output selection stage, decision based adaptive windowing concept is include for better impulse noise suppression and edge preservation. The extensive results for proposed architecture are shown better performance than any state-of-art method and some recently proposed work inclusive quantity and visual quality. The processing rate of our architecture is 254 MHz by using Vertex 5 FPGA board. Low computational complexity and no line buffer are needed. Its cost is comparably low and applicable to real time applications, i.e medical image processing.