Static test sequence compaction based on segment reordering and accelerated vector restoration

Vector restoration based static compaction techniques report significant compaction. In this paper we propose a new technique for static compaction which gives comparable or better compaction and runs 10 to 50 times faster than the fastest method. The new technique solves the problem of compaction by dividing it into small subproblems (referred to as segments). The solutions to these segments (or subproblems) are then dynamically merged providing excellent speed up without compromising on compaction efficiency. Further speed up is achieved by compacting the individual segments using an accelerated vector-restoration based compaction technique. If a fault requires a sequence of length n to be detected, in our approach the number of vectors that need to be simulated for restoring the sequence is O(n logan), while the prevailing approaches require simulation on O(n/sup 2/) vectors. Experimental results demonstrate substantial speedups compared to the prevailing vector restoration based techniques, while giving comparable or better compaction. When compared to the fastest method, our method was 5 to 30 times faster on ISCAS circuits and 10 to 50 times faster on real-life production circuits. For example, on one of the production circuits, our method gave 27 percent compaction in 188 seconds, while an improved version of the fastest method gave 25 percent compaction in 10200 seconds. In addition, our method could successfully process large industrial designs which could not be completed by earlier techniques in 2 CPU days.