A 500-MHz, 0.76-W/mm Power Density and 76.2% Power Efficiency, Fully Integrated Digital Buck Converter in 65-nm CMOS

In this paper, we propose a 500-MHz ON-chip digitally controlled buck converter in which active and passive components are fully integrated on a single CMOS chip. To achieve high-power density, a two-phase interleaving buck converter with negatively coupled inductors is adopted to reduce the silicon area for both inductors and output capacitors. In addition, the proposed ON-chip stacked L/C structure can achieve 20% area saving. Furthermore, to support a 500-Hz switching frequency, we present a low-power digital pulsewidth modulation (PWM) controller that includes a 9-bit time-based analog-to-digital converter and a 15%-90% wide-range digital pulsewidth modulator (DPWM), which occupies only 0.075 mm
²
and dissipation of 3 mW. The prototype IC fabricated in 65-nm CMOS can convert a 2.2-V input to a 1.2-V output and achieve a peak power efficiency of 76.2% and maximum power density of 0.76 W/mm
²
. Simultaneously, it can deliver 0.84 W and occupy 1.1 mm
²
of effective area that includes a pair of 1.54-nH ON-chip inductors and 2.63-nF ON-chip capacitors.