Guest Editorial IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

The papers in this special section focus on the technology and applications supported by defect/fault tolerance in very large scale integration and nanotechnology systems. With increasing demand for ever smaller, portable, energy-efficient, and high-performance electronic systems, scaling of CMOS technology continues. As CMOS scaling approaches physical limits, continued innovation in materials, manufacturing processes, device structures, and design paradigms have been necessary. High-κ oxide and metal-gate stack were introduced to address oxide leakage; thin body undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage; restricted design rules were introduced to improve layout efficiency; yet CMOS technology continues to be challenged in the areas of device aging and reliability. While CMOS is expected to be the dominant semiconductor technology for the foreseeable future—due to for reasons that are both technological and financial, alternatives to CMOS technology are attracting attention from the researchers.