Access pattern based multi-layer bus virtualization controller

To prove Moore's law, the future multi-core architecture will have a vast number of heterogeneous processors, memories, and analog components. Network on a chip architecture is not appropriate for such systems due to high latency issues. With the increase of processor cores, the systems face address translation delay, data management delay and timing issues. In this article, we intended to develop a high-performance and low-power network on chip architecture called Pattern based Network Virtualization Controller (PNVC). The PNVC uses pattern descriptor that handles on-chip data communication and manages multiple bus systems. The pattern descriptors permit the programmer to define the structure of data access patterns and the number of buses which reduces the data access latency. An intelligent algorithm that manages the different data transfer patterns. To validate the suggested controller performance, we execute it on a Xilinx Virtex-7 FPGA VC707 board. To verify that the controller is capable of a variety of scenarios, we perform the different experiment. The results show that PNVC consumes 1.9x fewer hardware resources, improves bus bandwidth up to 1.68 times and achieves a maximum speedup of 3.64 for various application kernels.