Precise register allocation for irregular architectures

This paper proposes a precise approach to register allocation for irregular-register architectures which is based on 0-1 integer programming (IP). Prior work shows that IP register allocation is feasible for RISC architectures, which have uniform registers and register usage. Extensions to the prior work are proposed that precisely model register irregularities including combined source/destination specifiers, memory operands, and variations in the cost of register usage. The x86 architecture is selected as a representative irregular-register architecture for experimental study. An IP register allocator is built for the x86 architecture within the Gnu C Compiler (GCC), and is compared experimentally with GCC's graph-coloring register allocator. Experimental results show that the IP allocator reduces register allocation overhead by 61% compared with the graph coloring allocator. The results also show that the x86 IP allocator is dramatically faster than the prior RISC IP allocator; because of the smaller number of registers in the x86 architecture and because of the register irregularities. These results suggest that IP register allocation is well suited for irregular-register architectures.