DRAM bit-line coupling noise analysis and simulation of process sensitivity for COB scheme

The bit-line coupling capacitance and the process sensitivity of the 8F/sup 2/ cell in the COB scheme are critical issues for future advanced DRAM. In this paper, these issues and design curves of bit-line coupling capacitance of an 8F/sup 2/ cell in the COB scheme are investigated by 3D simulation and an analytical model.