Triple modular redundancy on parallel-operation-oriented FPGA architectures for optical communications

Recently, high-speed space optical communication requires real-time hardware operation instead of slow software operation on a processor. For such purposes, field programmable gate arrays (FPGAs) are extremely useful. In such hardware accelerations, a software algorithm is frequently implemented onto an FPGA as a parallel operation. However, in such implementations, many regions of the configuration memory on an FPGA must have common circuit information, but the overlap on the configuration memory can be regarded as wasteful implementation. Therefore, a parallel-operation-oriented FPGA has been proposed to implement parallel operations onto an FPGA efficiently. Such a parallel-operation-oriented FPGA has numerous programmable gate array layers sharing a common configuration context so that the overlap data on the configuration memory of an FPGA can be removed perfectly. However, in space environments, triple modular redundancy must always be used to remove soft errors and the single shared configuration architecture of the parallel-operation-oriented FPGA is the opposite way of such redundancy. To meet those demands, we propose a suitable implementation method of triple modular redundancy (TMR) onto the parallel-operation-oriented FPGA architecture.