A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System

A fixed-point squaring algorithm is formulated and implemented based on an approach that allows any number of bits to be computed in each iterative step. The primary contribution this new approach offers is the ability for a designer to change the area × latency product through the choice of a different radix or number of bits per subword to be processed in each iterative step. When the number of subword bits is increased, latency is reduced since fewer iterations are required whereas the area is increased due to the larger subcircuit for squaring each subword. Alternatively, choosing a smaller subword or radix decreases area at the expense of increasing latency since more iterations are required. The subword size can range from a single bit yielding a bit-serial squarer requiring N iterations for an N-bit operand or “squarand,” to using the entire squarand resulting in a fully parallel squarer requiring no iterations. Because each m-bit subword can be considered a single digit in a number system with radix 2
^m
, the squarer presented here can be considered a multiple-valued logic (MVL) digit-serial architecture. This methodology allows for technologies based on any radix of two or greater to be used, including emerging technologies, thus yielding a true multiple-valued logic squaring circuit. The algorithm is derived through the generalization of a Vedic technique where any arbitrary integer-valued radix is used. Prototype hardware implementations using both a standard cell ASIC and FPGA technologies are developed. The prototype circuits are analyzed in terms of required resources and throughput characteristics and compared to a well-known prior art squaring circuit.