8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring

Signaling over chip-scale global interconnect is consuming a larger fraction of total power in large processor chips, as processes continue to shrink. Solving this growing crisis requires simple, low-energy and area-efficient signaling for high-bandwidth data buses. This paper describes a balanced charge-recycling bus (BCRB) that achieves quadratic power savings, relative to signaling with full-swing CMOS repeaters. The scheme stacks two CMOS repeated wire links, one operating in the Vtop domain, between Vdd and Vmid=Vdd/2, the other, Vbot, between Vmid and GND. Unlike previous work [1], we require no voltage regulator to maintain the Vmid voltage at Vdd/2, to compensate for differences in data activity in Vtop and Vbot domains. The BCRB also uses simple single-ended signaling, to achieve higher bandwidth per unit bus width than differential buses [2] and lower signaling energy than precharging schemes [3], since we take full advantage of low switching activity and bus-invert coding.