6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters

There is an increasing demand for high-reality video systems. The ITU-R has standardized video parameters for ultra-high-definition TV (UHDTV), and the full-specification video signal stated in this international standard is prescribed as having a 7,680 (H) × 4,320 (V) pixel count, 120Hz frame frequency with progressive scanning, 12b tone reproduction, and wide color gamut. A 33Mpixel 120fps CMOS image sensor with a 12b column-parallel analog-to-digital converter (ADC) is reported in [1]. In addition to standard operation, higher sensitivity, smaller pixels, and a higher frame rate of 240fps or more are required for CMOS image sensors. Backside-illuminated stacked CMOS image sensors [2] are effective for simultaneously achieving both high sensitivity for small pixels and high operation speed. However, these stacked structures are still insufficient for high-frame-rate UHDTV image sensors since the pixel wafer and the ASIC wafer are connected by through-silicon vias in the peripheral area.