2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner

Ring-VCOs (RVCOs) [1] have been avoided for over a decade for high-performance RF systems due to their much lower FOM (<;165dB [2]) than that of their LC counterparts from low to high frequency offsets. Yet, as the cost of ultra-scaled CMOS technologies is escalating, the small-die-area and wide-tuning-range advantages of RVCOs have attracted more attention recently, aiming to break the FOM limit at the system level. In [2], a type-I PLL succeeds in suppressing the RVCO phase noise (PN) by extending the loop bandwidth to 10MHz (f
_ref
/20 → f
_ref
/2), facilitating an ultra-compact (0.015mm
²
) frequency synthesizer for 2.4GHz WLAN. However, the type-I PLL only offers 20dB/dec phase-noise suppression for its RVCO. Thus, despite using large transistors (36/0.28μm), the 1/f
³
PN corner (f
₁
/f
₃
) is still high (~4MHz), degrading the overall jitter performance of the PLL. This paper proposes a dual-mode time-interleaved RVCO (TI-RVCO). It offers interesting properties of extending the frequency tuning range and reducing f1/f3 corner (~1MHz → ~100kHz), resulting in a better FOM over a wide range of frequency offsets (10kHz to 1MHz). The achieved f
₁
/f
₃
noise corner (~90kHz to 150kHz) is comparable to the state-of-the-art LC-VCOs [3, 4].