2.4 A 2-to-16GHz BiCMOS ΔΣ fractional-N PLL synthesizer with integrated VCOs and frequency doubler for wireless backhaul applications

The flourishing of ubiquitous wireless communication networks has pushed the development and deployment of complex RF telecom systems. Concurrently, the IC industry has been making an effort to increase the integration of RF devices. While nanometer CMOS technologies are now dominating end-user devices, the RF domain of wireless infrastructure still suffers from low-scale of integration [1]. Nonetheless, wireless backhaul vendors are now upgrading existing systems, which rely on expensive discrete technologies (i.e. GaAs), and adopting BiCMOS RFICs. A local oscillator (LO) synthesizer is a key block in the implementation of any wireless transceivers. Very tight requirements, in terms of frequency stability and phase noise performance, have led to complex PLL-based monolithic synthesizers. For instance, multi-bit capacitor array VCOs allow the reduction of the VCO tuning gain (Kvco), improving phase-noise performance without frequency coverage penalties. A ΔΣ fractional-N approach has been also introduced to optimize frequency resolution, lock time and noise performance of PLL-based synthesizers [2].