Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks

This paper presents algorithms and hardware implementations of associative memories based on multiple-valued sparse clustered networks (MV-SCNs). SCNs are recently-introduced binary-weighted associative memories that significantly improve the storage and retrieval capabilities over the prior state-of-the art. However, deleting or updating the messages stored in binary-weighted connections result in a significant increase in the data retrieval error probability as the binary-weighted connections deleted may be shared for several data patterns. In order to address the problem, the proposed algorithm exploits multiple-valued weighted connections of the network for storing the messages while maintaining the number of computation nodes in a cluster. The use of the multiple-valued weighted connections reduces the probability of deleting the shared connections compared to the binary-weighted connections. As a result, the proposed algorithm lowers the error rate by an order of magnitude for our sample network with 60% deleted contents compared to the conventional algorithm when the same amount of memory is used. For performance comparisons in hardware, the proposed SCNs are designed using Verilog-HDL and synthesized on TSMC 65 nm CMOS technology. The synthesis results show that the proposed MV-SCNs are around 10% smaller than the conventional binary-weighted SCNs as the number of computation nodes in the proposed SCNs is smaller than that of the conventional SCNs with the comparable speed and memory size.