A BIST scheme for asynchronous logic

This work introduces a methodology to ease the implementation of BIST in asynchronous circuits. Scheduling by edge reversal (SER), a simple but powerful distributed synchronizer is used to implement a sequencer that allows testing the circuit at full speed. The methodology, which allows the detection of topological faults, is proved correct. Low hardware overhead and the absence of deadlocks are the main characteristics of the proposed methodology.