Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

For the first time, the interest of a new SiCO low-k spacer material deposited at 400°C is evaluated in the perspective of a 3D VLSI integration. The benefits of SiCO low-k (4.5 vs 7 for SiN) value is preserved throughout the whole integration and translates into a 5% decrease for both effective capacitance and delay of FO3 Ring Oscillators in a 14FDSOI technology. In addition, a NMOS breakdown voltage improvement of 3.5V and a decrease in leakage current of 0.7 decade is demonstrated on thick oxide devices. This electrical performance together with the low temperature deposition makes SiCO a very appealing candidate for 3D VLSI in a CoolCube™ integration scheme.