Abstract:
NAND Flash has followed Moore's law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue...Show MoreMetadata
Abstract:
NAND Flash has followed Moore's law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue the scaling. This paper describes a floating gate based 3D NAND technology with superior cell characteristics relative to 2D NAND, and CMOS under array for high Gb/mm2 density.
Published in: 2015 IEEE International Electron Devices Meeting (IEDM)
Date of Conference: 07-09 December 2015
Date Added to IEEE Xplore: 18 February 2016
ISBN Information:
Electronic ISSN: 2156-017X
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