First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

The first monolithic integration of Ge p-FETs and InAs n-FETs on silicon substrate using a sub-120 nm III-V buffer technology is reported. A common digital etch process was developed to precisely control the etching of InAs and Ge, enabling the realization of Ge p-FETs and InAs n-FETs with a body thickness T
_body
of below 5 nm and channel lengths L
_CH
smaller than 200 nm. Other process modules such as common gate stack and contact processes were also employed. By comparing with other reports that co-integrated Si
_1-x
Ge
_x
p-FETs and In
_x
Ga
_1-x
As n-FETs on Si or Ge substrates, the Ge p-FETs and InAs n-FETs in this work achieve the highest drive current ION.