An improved drain-current-conductance method with substrate back-biasing

A previously developed drain-current-conductance method (DCCM) is extended to investigate the effect of back-bias on LATID NMOSFETs. For the same effective gate overdrive, the extracted drain and source series resistances increase as the back-bias is increased. Two-dimensional device simulation showed that the increased back-bias results in reduced current contour values at the drain/source regions as a result of the increase in the series resistances.