SESSION T2A: Tutorial: Advanced ESD protection design for CMOS circuits and systems

To reduce the weight of electronic products, to integrate more functions into the electronic products, as well as to reduce the power consumption of electronic products, the CMOS technology has been developed into nanometer scale to realize VLSI/SoC for electronic systems. With the transistors in the nano-scale dimension, the gate-oxide thickness of MOSFET is only 10~15Å for operating with sub-1V power supply. Such thinner gate oxide is very easily ruptured by electrostatic discharge (ESD) events, which frequently happen in our environments with the voltage level of hundreds or even thousands volts. The integrated circuits (ICs) are weaker to sustain such ESD stresses during the assembly, testing, package, and the applications. To verify the ESD reliability of IC products for safe applications, there are already some industry ESD test standards developed, such as Human Body Model (HBM) and Charged Device Model (CDM), to verify the ESD robustness of IC products. Besides, in the IEC 61000-4-2 standard, the electronic products are zapped by the ESD gun with ESD voltage of even up to 15kV in the air-discharge mode. How to design the on-chip ESD protection circuits to effectively protect the integrated circuits realized by the nano-scale CMOS devices is a quite difficult challenge to IC industry. The on-chip ESD protection circuit must be included in the beginning phase of chip design. In this Tutorial, a brief introduction on ESD issue and test standards to IC products is presented with some failure analysis pictures from real IC products to demonstrate the impact of ESD on IC products. The basic design concept for on-chip ESD protection circuit will be presented. Some useful ESD protection designs for high-speed I/O and RF circuits will be mentioned. To achieve the whole-chip ESD protection by using the active power-rail ESD clamp circuit will be emphasized. Additional consideration on the active power-rail ESD clamp circuit realized in the nanoscale CMOS processes will be especially addressed. After the component-level ESD protection, the system-level ESD protection design will be brief discussed. ESD protection for CMOS ICs is not only the process issue but also highly dependent to the design issue, which has been an important topic that the IC designers need to know.