Design for manufacturing and reliability for nanometer SoCs (system-on-chips)

As the device dimension increases and chip sizes shrink, on-chip semiconductor process variation can no longer be ignored in the design and signoff static timing analysis of integrated circuits. Thus, we need to ensure not only conventional design closure but also manufacturing closure in nanometer regime. As it has been shown that manufacturing issues are strongly layout dependent, manufacturability aware layout optimization for manufacturing closure shall play a key role in the overall yield improvement. In this paper, we will discuss many manufacturability, variability, reliability, and power aware efforts in design stages for nanometer node SoCs (system-on-chips).