A switch-decoded current-steering DAC

A switch-decoded based current-steering architecture is proposed for calibration DAC of ADCs. The circuit and working principle of the proposed switch-decoded current-steering DAC is introduced. A 14-bit DAC is realized in 0.18um CMOS process by combining an 8-bit switch-decoded current-steering DAC with a 6-bit binary-weight DAC. The chip area taken by the 14-bit DAC is only 0.1 square millimeters. The simulation shows that the DNL is +0.18/-0.52LSB and the INL is +1.5/-2.3LSB.