Digital Calibration of DAC Unit Elements Mismatch in Pipelined ADCs

This paper presents a statistics-based digital background calibration technique for digital-to-analog converter (DAC) unit elements mismatch in pipelined analog-to-digital converters (ADCs). The proposed calibration method continuously measures and digitally mitigates sub-DAC (SDAC) mismatch errors in background during the normal data-conversion operation. In this method, the probability density function (PDF) of the sub-ADC (SADC) quantization error is analyzed using a two-level pseudorandom noise (PN) sequence in order to extract and remove SDAC mismatch errors. Behavioral simulation results are provided for a 12-bit pipelined ADC architecture to validate the effectiveness of the introduced method. Simulation results show that the signal-to-noise and distortion ratio (SNDR) is improved from 48.4 dB to 70.2 dB using the proposed calibration technique. This scheme converges after approximately $30\times 10^{6}$ clock cycles.